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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad5306/ad5316/ad5326 * 2.5 v to 5.5 v, 400 a, 2-wire interface, quad voltage output, 8-/10-/12-bit dacs * protected by u.s. patent numbers 5,969,657 and 5,684,481. features ad5306: 4 buffered 8-bit dacs in 16-lead tssop a version: 1 lsb inl, b version: 0.625 lsb inl ad5316: 4 buffered 10-bit dacs in 16-lead tssop a version: 4 lsb inl, b version: 2.5 lsb inl ad5326: 4 buffered 12-bit dacs in 16-lead tssop a version: 16 lsb inl, b version: 10 lsb inl low power operation: 400 a @ 3 v, 500 a @ 5 v 2-wire (i 2 c compatible) serial interface 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 90 na @ 3 v, 300 na @ 5 v ( pd pin or bit) double-buffered input logic buffered/unbuffered reference input options output range: 0 v to v ref or 0 v to 2 v ref power-on reset to 0 v simultaneous update of outputs ( ldac pin) software clear facility data readback facility on-chip rail-to-rail output buffer ampli?rs temperature range ?0 c to +105 c functional block diagram input register v out a buffer string dac a v dd ad5306/ad5316/ad5326 v out b buffer string dac b v out c buffer string dac c v out d buffer string dac d gain-select logic v ref a scl a0 pd power-on reset power-down logic ldac ldac sda a1 v ref b dac register input register dac register input register dac register input register dac register interface logic v ref dv ref c gnd general description the ad5306/ad5316/ad5326 are quad 8-, 10-, and 12-bit buffered voltage output dacs in a 16-lead tssop that operate from a single 2.5 v to 5.5 v supply, consuming 500 a at 3 v. their on-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 v/ s. a 2-wire serial interface that operates at clock rates up to 400 khz is used. this interface is smbus compatible at v dd < 3.6 v. multiple devices can be placed on the same bus. each dac has a separate reference input that can be configured as buffered or unbuffered. the outputs of all dacs may be updated simultaneously using the asynchronous ldac input. the parts incorporate a power-on reset circuit, which ensures that the dac outputs power up to 0 v and remain there until a valid write to the device takes place. there is also a software clear function that clears all dacs to 0 v. the parts contain a power-down feature that reduces the current consumption of the device to 300 na @ 5 v (90 na @ 3 v). all three parts are offered in the same pinout, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board. applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control
rev. c ? ad5306/ad5316/ad5326?pecifications (v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all speci?ations t min to t max , unless otherwise noted.) a version 2 b version 2 parameter 1 min typ max min typ max unit conditions/comments dc performance 3, 4 ad5306 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.625 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5316 resolution 10 10 bits relative accuracy 0.5 4 0.5 2.5 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5326 resolution 12 12 bits relative accuracy 2 16 2 10 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 5 60 5 60 mv v dd = 4.5 v, gain = 2; see figures 2 and 3 gain error 0.3 1.25 0.3 1.25 % of fsr v dd = 4.5 v, gain = 2; see figures 2 and 3 lower deadband 5 10 60 10 60 mv see figure 2; lower deadband exists only if offset error is negative. upper deadband 5 10 60 10 60 mv see figure 3; upper deadband exists only if v ref = v dd and offset plus gain error is positive. offset error drift 6 ?2 12 ppm of fsr/ c gain error drift 6 ? ? ppm of fsr/ c dc power supply rejection ratio 6 ?0 60 db v dd = 10% dc crosstalk 6 200 200 m vr l = 2 k w to gnd or v dd dac reference inputs 6 v ref input range 1 v dd 1v dd v buffered reference mode 0.25 v dd 0.25 v dd v unbuffered reference mode v ref input impedance >10 >10 m w buffered reference mode and power-down mode 148 180 148 180 k w unbuffered reference mode. 0 v to v ref output range 74 90 74 90 k w unbuffered reference mode. 0 v to 2 v ref output range reference feedthrough ?0 90 db frequency = 10 khz channel-to-channel isolation ?5 75 db frequency = 10 khz output characteristics 6 minimum output voltage 7 0.001 0.001 v this is a measure of the minimum and maximum drive capability maximum output voltage 7 v dd ?0.001 v dd ?0.001 v of the output ampli?r. dc output impedance 0.5 0.5 w short circuit current 25 25 ma v dd = 5 v 16 16 ma v dd = 3 v power-up time 2.5 2.5 m s coming out of power-down mode. v dd = 5 v 55 m s coming out of power-down mode. v dd = 3 v logic inputs (excluding scl, sda) 6 input current 1 1 m a v il , input low voltage 0.8 0.8 v v dd = 5 v 10% 0.6 0.6 v v dd = 3 v 10% 0.5 0.5 v v dd = 2.5 v v ih , input high voltage 1.7 1.7 v v dd = 2.5 v to 5.5 v; ttl and 1.8 v cmos compatible pin capacitance 3 3 pf
rev. c ad5306/ad5316/ad5326 ? ac characteristics 1 a version 2 b version 2 parameter 1 min typ max min typ max unit conditions/comments logic inputs (scl, sda) 6 v ih , input high voltage 0.7 v dd v dd + 0.3 0.7 v dd v dd + 0.3 v smbus compatible at v dd < 3.6 v v il , input low voltage ?.3 0.3 v dd ?.3 0.3 v dd vs mbus compatible at v dd < 3.6 v i in , input leakage current 1 1 m a v hyst , input hysteresis 0.05 v dd 0.05 v dd v see tpc 15 c in , input capacitance 8 8 pf glitch rejection 50 50 ns input filtering suppresses noise spikes of less than 50 ns. logic output (sda) 6 v ol , output low voltage 0.4 0.4 v i sink = 3 ma 0.6 0.6 v i sink = 6 ma three-state leakage current 1 1 m a three-state output capacitance 8 8 pf power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 8 v ih = v dd and v il = gnd. interface inactive v dd = 4.5 v to 5.5 v 500 900 500 900 m a all dacs in unbuffered mode. buffered mode, extra current v dd = 2.5 v to 3.6 v 400 750 400 750 m a is typically x m a per dac where x = 5 m a + v ref /r dac . i dd (power-down mode) v ih = v dd and v il = gnd. interface inactive v dd = 4.5 v to 5.5 v 0.3 1 0.3 1 m ai dd = 3 m a (max) during readback on sda v dd = 2.5 v to 3.6 v 0.09 1 0.09 1 m ai dd = 1.5 m a (max) during 0 readback on sda notes 1 see the terminology section. 2 temperature range (a, b version): ?0 c to +105 c; typical at +25 c. 3 dc speci?ations tested with the outputs unloaded. 4 linearity is tested using a reduced code range: ad5306 (code 8 to 255); ad5316 (code 28 to 1023); ad5326 (code 115 to 4095). 5 this corresponds to x codes. x = deadband voltage/lsb size. 6 guaranteed by design and characterization; not production tested. 7 for the ampli?r output to reach its minimum voltage, offset error must be negative; for the ampli?r output to reach its maxim um voltage, v ref = v dd and offset plus gain error must be positive. 8 interface inactive; all dacs active. dac outputs unloaded. speci?ations subject to change without notice. (v dd = 2.5 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; all speci?ations t min to t max , unless otherwise noted.) a, b version 3 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5306 6 8 m s 1/4 scale to 3/4 scale change (0x40 to 0xc0) ad5316 7 9 m s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5326 8 10 m s 1/4 scale to 3/4 scale change (0x400 to 0xc00) slew rate 0.7 v/ m s major-code change glitch energy 12 nv-s 1 lsb change around major carry digital feedthrough 0.5 nv-s digital crosstalk 0.5 nv-s analog crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p, unbuffered mode total harmonic distortion ?0 db v ref = 2.5 v 0.1 v p-p, frequency = 10 khz notes 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range (a, b version): ?0 c to +105 c; typical at +25 c. speci?ations subject to change without notice.
rev. c ? ad5306/ad5316/ad5326 timing characteristics 1 (v dd = 2.5 v to 5.5 v; all speci?ations t min to t max , unless otherwise noted.) a, b version parameter 2 limit at t min , t max unit conditions/comments t 1 2.5 m s min scl cycle time t 2 0.6 m s min t high , scl high time t 3 1.3 m s min t low , scl low time t 4 0.6 m s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 3 0.9 m s max t hd,dat , data hold time 0 m s min t 7 0.6 m s min t su,sta , setup time for repeated start t 8 0.6 m s min t su,sto , stop condition setup time t 9 1.3 m s min t buf , bus free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 250 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1c b 4 ns min t f , fall time of scl and sda when transmitting t 12 20 ns min ldac pulsewidth t 13 400 ns min scl rising edge to ldac rising edge c b 400 pf max capacitive load for each bus line notes 1 see figure 1. 2 guaranteed by design and characterization; not production tested. 3 a master device must provide a hold time of at least 300 ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of scl? falling edge. 4 c b is the total capacitance of one bus line in pf. t r and t f measured between 0.3 v dd and 0.7 v dd . specifications subject to change without notice. scl sda t 9 t 4 t 6 t 2 t 5 t 7 t 8 t 1 t 11 t 10 t 3 t 12 ldac 1 ldac 2 start condition repeated start condition stop condition notes 1 asynchronous ldac update mode. 2 synchronous ldac update mode. t 4 t 12 t 13 figure 1. 2-wire serial interface timing diagram
rev. c ad5306/ad5316/ad5326 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5306/ad5316/ad5326 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = 25 c, unless otherwise noted.) v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +7 v scl, sda to gnd . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v a0, a1, ldac , pd to gnd . . . . . . . . ?.3 v to v dd + 0.3 v reference input voltage to gnd . . . . ?.3 v to v dd + 0.3 v v out a? to gnd . . . . . . . . . . . . . . . ?.3 v to v dd + 0.3 v operating temperature range industrial (a, b version) . . . . . . . . . . . . . ?0 c to +105 c storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature (t j m ax) . . . . . . . . . . . . . . . . . . . 150 c ordering guide model temperature range package description package option ad5306aru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5306aru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5316aru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 AD5316ARU-REEL7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5326aru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5326aru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5306bru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5306bru-reel ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5306bru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5316bru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5316bru-reel ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5316bru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5326bru ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5326bru-reel ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 ad5326bru-reel7 ?0 c to +105 ct hin shrink small outline package (tssop) ru-16 16-lead tssop power dissipation . . . . . . . . . . . . . . . . . . (t j m ax ?t a )/ ja ja thermal impedance . . . . . . . . . . . . . . . . . . . 150.4 c/w reflow soldering peak temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c time at peak temperature . . . . . . . . . . . . . 10 sec to 40 sec notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci?ation is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2 transient currents of up to 100 ma will not cause scr latch-up.
rev. c ? ad5306/ad5316/ad5326 pin configuration top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 ldac v dd v ref b v ref a v out a a0 gnd scl v out d pd ad5306/ ad5316/ ad5326 v out b v out c v ref c v ref d sda a1 pin function descriptions pin no. mnemonic function 1 ldac active low control input that transfers the contents of the input registers to their respective dac registers. pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows simultaneous update of all dac outputs. alternatively, this pin can be tied permanently low. 2v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and the supply should be decoupled with a 10 m f capacitor in parallel with a 0.1 m f capacitor to gnd. 3v out ab uffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 4v out bb uffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 5v out cb uffered analog output voltage from dac c. the output amplifier has rail-to-rail operation. 6v ref ar eference input pin for dac a. it may be configured as a buffered or an unbuffered input depending on the state of the buf bit in the input word to dac a. it has an input range from 0.25 v to v dd in unbuf- fered mode and from 1 v to v dd in buffered mode. 7v ref br eference input pin for dac b. it may be configured as a buffered or an unbuffered input depending on the state of the buf bit in the input word to dac b. it has an input range from 0.25 v to v dd in unbuf- fered mode and from 1 v to v dd in buffered mode. 8v ref cr eference input pin for dac c. it may be configured as a buffered or an unbuffered input depending on the state of the buf bit in the input word to dac c. it has an input range from 0.25 v to v dd in unbuf- fered mode and from 1 v to v dd in buffered mode. 9v ref dr eference input pin for dac d. it may be configured as a buffered or an unbuffered input depending on the state of the buf bit in the input word to dac d. it has an input range from 0.25 v to v dd in unbuf- fered mode and from 1 v to v dd in buffered mode. 10 pd active low control input that acts as a hardware power-down option. all dacs go into power-down mode when this pin is tied low. the dac outputs go into a high impedance state. the current consump- tion of the part drops to 300 na @ 5 v (90 na @ 3 v). 11 v out db uffered analog output voltage from dac d. the output amplifier has rail-to-rail operation. 12 gnd ground reference point for all circuitry on the part. 13 sda serial data line. this is used in conjunction with the scl line to clock data into the 16-bit input shift register. it is a bidirectional open-drain data line that should be pulled to the supply with an external pull- up resistor. 14 scl serial clock line. this is used in conjunction with the sda line to clock data into the 16-bit input shift register. clock rates of up to 400 kbit/s can be accommodated in the i 2 c compatible interface. 15 a0 address input. sets the lsb of the 7-bit slave address. 16 a1 address input. sets the second lsb of the 7-bit slave address.
rev. c ad5306/ad5316/ad5326 ? terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer func tion. typical inl versus code plots can be seen in tpcs 1, 2, and 3. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a speci?d differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. typical dnl versus code plots can be seen in tpcs 4, 5, and 6. offset error this is a measure of the offset error of the dac and the output ampli?r. it can be positive or negative. see figures 2 and 3. it is expressed in mv. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is mea- sured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac at m idscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in m v. reference feedthrough this is the ratio of the amplitude of the signal at the dac out- put to the reference input when the dac output is not being updated (i.e., ldac is high). it is expressed in db. channel-to-channel isolation this is the ratio of the amplitude of the signal at the output of one dac to a sine wave on the reference input of another dac. it is measured in db. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac regis- ter changes state. it is normally speci?d as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device when the dac output is not being updated. it is specified in nv-s and is measured with a worst-case change on the digital input pins, i.e., from all 0s to all 1s or vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv-s. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the energy of the glitch is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with ldac low and moni- toring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the ampli?rs within the dac have a ?ite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at w hich the output amplitude falls to 3 db below the input. total harmonic distortion this is the difference between an ideal sine wave and its attenu ated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in db.
rev. c ? ad5306/ad5316/ad5326 gain error + offset error output voltage negative offset error dac code negative offset error amplifier footroom lower deadband codes actual ideal figure 2. transfer function with negative offset output voltage positive offset error dac code gain error + offset error actual ideal upper deadband codes full scale figure 3. transfer function with positive offset (v ref = v dd )
rev. c t ypical performance characteristics?d5306/ad5316/ad5326 ? code inl error (lsb) 1.0 0.5 ?.0 050 250 100 150 200 0 ?.5 t a = 25 c v dd = 5v tpc 1. ad5306 typical inl plot code dnl error (lsb) 050 250 100 150 200 ?.1 ?.2 ?.3 0.3 0.1 0.2 0 t a = 25 c v dd = 5v tpc 4. ad5306 typical dnl plot v ref (v) error (lsb) 0.50 0.25 ?.50 01 5 234 0 ?.25 max inl max dnl min dnl min inl t a = 25 c v dd = 5v tpc 7. ad5306 inl and dnl error vs. v ref code inl error (lsb) 3 0 200 1000 400 600 800 0 ? ? ? 2 1 t a = 25 c v dd = 5v tpc 2. ad5316 typical inl plot code dnl error (lsb) 0.4 ?.4 600 400 800 1000 0 ?.6 0.6 0.2 ?.2 t a = 25 c v dd = 5v 200 0 tpc 5. ad5316 typical dnl plot temperature ( c) error (lsb) 0.5 0.2 ?.5 40 0 40 0 ?.2 80 120 ?.4 ?.3 ?.1 0.1 0.3 0.4 v dd = 5v v ref = 3v max inl max dnl min dnl min inl tpc 8. ad5306 inl and dnl error vs. temperature code inl error (lsb) 12 0 ? ? 8 4 0 4000 1000 2000 3000 ?2 t a = 25 c v dd = 5v tpc 3. ad5326 typical inl plot code dnl error (lsb) 0.5 2000 3000 4000 0 ?.0 1.0 ?.5 t a = 25 c v dd = 5v 1000 0 tpc 6. ad5326 typical dnl plot gain error temperature ( c) error (% fsr) 1.0 0.5 ?.0 40 0 40 0 ?.5 v dd = 5v v ref = 2v offset error 80 120 tpc 9. ad5306 offset error and gain error vs. temperature
rev. c ?0 ad5306/ad5316/ad5326 v dd (v) error (% fsr) 0.2 ?.6 01 3 0 ?.4 46 ?.5 ?.3 ?.2 ?.1 0.1 25 offset error gain error t a = 25 c v ref = 2v tpc 10. offset error and gain error vs. v dd v dd (v) i dd ( a) 600 2.5 500 400 300 200 100 0 3.0 3.5 4.0 4.5 5.0 5.5 ?0 c +25 c +105 c tpc 13. supply current vs. supply voltage v out a t a = 25 c v dd = 5v v ref = 5v ch1 ch2 scl ch1 1v, ch2 5v, time base = 1 s/div tpc 16. half-scale settling (1/4 to 3/4 scale code change) sink/source current (ma) v out (v) 5 0 01 3 4 46 1 2 3 25 5v source 3v source 5v sink 3v sink tpc 11. v out vs. source and sink current capability v dd (v) i dd ( a) 0.5 0 0.4 0.1 0.2 0.3 2.5 3.0 4.0 4.5 5.5 3.5 5.0 ?0 c +25 c +105 c tpc 14. power-down current vs. supply voltage v out a t a = 25 c v dd = 5v v ref = 2v ch1 ch2 ch1 2.00v, ch2 200mv, time base = 200 s/div v dd tpc 17. power-on reset to 0 v code i dd ( a) 600 zero scale full scale 500 400 300 200 100 0 t a = 25 c v dd = 5v v ref = 2v tpc 12. supply current vs. dac code v logic (v) i dd ( a) 400 03 1 650 450 5 500 550 600 4 2 t a = 25 c v dd = 3v increasing decreasing increasing v dd = 5v decreasing tpc 15. supply current vs. logic input voltage for sda and scl voltage increasing and decreasing t a = 25 c v dd = 5v v ref = 2v ch1 ch2 ch1 500mv, ch2 5.00v, time base = 1 s/div v out a pd tpc 18. exiting power-down to midscale
rev. c ad5306/ad5316/ad5326 ?1 i dd ( a) frequency 350 400 500 550 450 600 v dd = 3v v dd = 5v tpc 19. i dd histogram with v dd = 3 v and v dd = 5 v v ref (v) full-scale error (v) 0.02 ?.02 01 3 0.01 ?.01 46 0 25 v dd = 5v t a = 25 c tpc 22. full-scale error vs. v ref 1 s /div 2.48 2.49 v out (v) 2.47 2.50 tpc 20. ad5326 major-code transition glitch energy 150ns/div 1mv/div tpc 23. dac-to-dac crosstalk frequency (hz) 10 ?0 10 ?0 ?0 0 ?0 db 100 1k 10k 100k 1m 10m ?0 ?0 tpc 21. multiplying bandwidth (small-signal frequency response) functional description the ad5306/ad5316/ad5326 are quad resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits, respectively. each contains four output buffer ampli?rs and is written to via a 2-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer am pli?rs provide rail-to-rail output swing with a slew rate of 0.7 v/ m s. each dac is provided with a separate reference input, which may be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from 0.25 v to v dd . the devices have a power-down mode in which all dacs may be turned off completely with a high impedance output. digital-to-analog section the architecture of one dac channel consists of a resistor- string dac followed by an output buffer ampli?r. the voltage at the v ref pin provides the reference voltage for the corresponding dac. figure 4 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by v vd out ref n = 2 where: d = decimal equivalent of the binary code that is loaded to the dac register: 0?55 for ad5306 (8 bits) 0?023 for ad5316 (10 bits) 0?095 for ad5326 (12 bits) n = dac resolution v out a gain mode (gain = 1 or 2) v ref a buf dac register input register resistor string output buffer amplifier reference buffer figure 4. single dac channel architecture
rev. c ?2 ad5306/ad5316/ad5326 resistor string the resistor string section is shown in figure 5. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output ampli?r. the voltage is tapped off by closing one of the switches connecting the string to the ampli?r. because it is a string of resistors, it is guaranteed monotonic. dac reference inputs there is a reference pin for each of the four dacs. the refer- ence inputs are buffered but can also be individually configured as unbuffered. the advantage with the buffered input is the high impedance it presents to the voltage source driving it. however, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 v and as high as v dd since there is no restriction due to headroom and footroom of the reference amplifier. r r r r r to output amplifier figure 5. resistor string if there is a buffered reference in the circuit (e.g., ref192), there is no need to use the on-chip buffers of the ad5306/ ad5316/ad5326. in unbuffered mode, the input impedance is still large at typically 180 k w per reference input for 0 v to v ref mode and 90 k w for 0 v to 2 v ref mode. the buffered/unbuffered option is controlled by the buf bit in the control byte. the buf bit setting applies to whichever dac is selected in the pointer byte. output ampli?r the output buffer amplifier is capable of generating output voltages to within 1 mv of either rail. its actual range depends on the value of v ref , gain, offset error, and gain error. if a gain of 1 is selected (gain = 0), the output range is 0.001 v to v ref . if a gain of 2 is selected (gain = 1), the output range is 0.001 v to 2 v ref . because of clamping, however, the maximum output is limited to v dd ?0.001 v. the output amplifier is capable of driving a load of 2 k w to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in the plot in tpc 11. the slew rate is 0.7 v/ m s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 m s. power-on reset the ad5306/ad5316/ad5326 are provided with a power-on reset function so that they power up in a de?ed state. the power-on state is normal operation reference inputs unbuffered 0 v to v ref output range output voltage set to 0 v both input and dac registers are ?led with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up. serial interface the ad5306/ad5316/ad5326 are controlled via an i 2 c compat- ible serial bus. these devices are connected to this bus as slave devices (i.e., no clock is generated by the ad5306/ ad5316/ ad5326 dacs). this interface is smbus compatible at v dd < 3.6 v. the ad5306/ad5316/ad5326 has a 7-bit slave address. the 5 msb are 00011 and the 2 lsb are determined by the state of the a0 and a1 pins. the facility to make hardwired changes to a0 and a1 allows the user to have up to four of these devices on one bus. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the ad dress byte, which consists of the 7-bit slave address followed by an r/ w bit (this bit determines whether data will be read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written to, a stop condition is established. in write mode, the master will pull the sda line high during the 10th clock pulse to establish a stop condition. in read mode, the master will issue a no acknowledge for the ninth clock pulse (i.e., the sda line re mains high). the master will then bring the sda line low before the 10th clock pulse and then high during the 10th clock pulse to establish a stop condition.
rev. c ad5306/ad5316/ad5326 ?3 read/write sequence in the case of the ad5306/ad5316/ad5326, all write access sequences and most read sequences begin with the device address (with r/ w = 0) followed by the pointer byte. this pointer byte specifies the data format and determines which dac is being accessed in the subsequent read/write operation. see figure 6. in a write operation, the data follows immediately. in a read operation, the address is resent with r/ w = 1 and the data is then read back. however, it is also possible to perform a read operation by sending only the address with r/ w = 1. the previously loaded pointer settings are then used for the readback operation. dacd xx lsb msb double = 0 dacc dacb daca left = 0 figure 6. pointer byte pointer byte bits the following is an explanation of the individual bits that make up the pointer byte. xd on? care bits. left 0: data written to the device and read from the de vice is left-justified. double 0: data write and readback are done as 2-byte write/read se quences. dacd 1: the following data bytes are for dac d. dacc 1: the following data bytes are for dac c. dacb 1: the following data bytes are for dac b. daca 1: the following data bytes are for dac a. input shift register the input shift register is 16 bits wide. data is loaded into the device as two data bytes on the serial data line, sda, under the control of the serial clock input, scl. the timing diagram for this operation is shown in figure 1. the two data bytes consist of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. the first bits loaded are the control bits: gain, buf, clr , and pd . the remaining bits are left-justified dac data bits, starting with the msb. see figure 7. gain 0: output range for that dac set at 0 v to v ref . 1: output range for that dac set at 0 v to 2 v ref . buf 0: reference input for that dac is unbuffered. 1: reference input for that dac is buffered. clr 0: all dac registers and input registers are filled with zeros on completion of the write sequence. 1: normal operation. pd 0: on completion of the write sequence, all four dacs go into power-down mode. the dac outputs enter a high impedance state. 1: normal operation. default readback conditions all pointer byte bits power up to 0. therefore, if the user ini- tiates a readback without first writing to the pointer byte, no single dac channel has been specified. in this case, the default readback bits are all 0 except for the clr bit and the pd bit, which are 1. multiple-dac write sequence because there are individual bits in the pointer byte for each dac, it is possible to write the same data and control bits to 2, 3, or 4 dacs simultaneously by setting the relevant bits to 1. multiple-dac readback sequence if the user attempts to read back data from more than one dac at a time, the part will read back the power-on condition of gain, buf, and data bits (all 0), and the current state of clr and pd . buf clr pd d7 d6 d5 d4 gain lsb msb 8-bit ad5306 buf clr pd d9 d8 d7 d6 gain buf d11 d10 d9 d8 gain most significant data byte data bytes (write and readback) lsb msb 10-bit ad5316 lsb msb 12-bit ad5326 clr pd least significant data byte d3 d2 d1 d0 x x x x d5 d4 d3 d2 d1 d0 x x d7 d6 d5 d4 d3 d2 d1 d0 lsb msb 8-bit ad5306 lsb msb 10-bit ad5316 lsb msb 12-bit ad5326 figure 7. data formats for write and readback
rev. c ?4 ad5306/ad5316/ad5326 write operation when writing to the ad5306/ad5316/ad5326 dacs, the user must begin with an address byte (r/ w = 0), after which the dac will acknowledge that it is prepared to receive data by pulling sda low. this address byte is followed by the pointer byte, which is also acknowledged by the dac. two bytes of data are then written to the dac, as shown in figure 8. a stop condition follows. read operation when reading data back from the ad5306/ad5316/ad5326 dacs, the user begins with an address byte (r/ w = 0), after which the dac will acknowledge that it is prepared to receive data by pulling sda low. this address byte is usually followed by the pointer byte, which is also acknowledged by the dac. following this, there is a repeated start condition by the master and the address is resent with r/ w = 1. this is acknowledged by the dac indicating that it is prepared to transmit data. two bytes of data are then read from the dac, as shown in figure 9. a stop condition follows. most significant data byte least significant data byte scl sda msb lsb msb lsb ack by ad53x6 ack by ad53x6 stop cond by master 0 0011 a0 r/ w xx lsb ack by ad53x6 ack by ad53x6 msb address byte start cond by master scl sda a1 pointer byte figure 8. write sequence most significant data byte scl sda msb lsb ack by ad53x6 ack by master repeated start cond by master address byte 00 0 11 a0 r/ w a1 0 0011 a0 r/ w xx lsb ack by ad53x6 ack by ad53x6 msb address byte start cond by master scl sda a1 pointer byte scl sda msb lsb no ack by master stop cond by master least significant data byte note: data bytes are the same as those in the write sequence, except that don't cares are read back as 0s. figure 9. readback sequence
rev. c ad5306/ad5316/ad5326 ?5 however, if the master sends an ack and continues clocking scl (no stop is sent), the dac will retransmit the same two bytes of data on sda. this allows continuous readback of data from the selected dac register. alternatively, the user may send a start followed by the address with r/ w = 1. in this case, the previously loaded pointer settings are used and readback of data can commence immediately. double-buffered interface the ad5306/ad5316/ad5326 dacs have double-buffered interfaces consisting of two banks of registers: input registers and dac registers. the input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac registers contain the digital code used by the resistor strings. access to the dac registers is controlled by the ldac pin. when ldac is high, the dac registers are latched and the input registers may change state without affecting the contents of the dac registers. when ldac is brought low, however, the dac registers become transparent and the contents of the input registers are transferred to them. double-buffering is useful if the user requires simultaneous updating of all dac outputs. the user may write to each of the input registers individually and then, by pulsing the ldac input low, all outputs will update simultaneously. these parts contain an extra feature whereby a dac register is not updated unless its input register has been updated since the last time that ldac was low. normally, when ldac is low, the dac registers are filled with the contents of the input regis- ters. in the case of the ad5306/ad5316/ad5326, the part will update the dac register only if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. load dac input ldac ldac transfers data from the input registers to the dac regis- ters (and, therefore, updates the outputs). use of the ldac function enables double-buffering of the dac data, gain, and buf. there are two ldac modes: synchronous mode: in this mode, the dac registers are updated after new data is read in on the rising edge of the eighth scl pulse. ldac can be tied permanently low or pulsed as in figure 2. asynchronous mode: in this mode, the outputs are not upd ated at the same time that the input registers are written to. when ldac goes low, the dac registers are updated with the con tents of the input registers. power-down mode the ad5306/ad5316/ad5326 have very low power consump- tion, dissipating typically 1.2 mw with a 3 v supply and 2.5 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into power-down mode, which is selected by setting the pd pin low or by setting bit 12 ( pd ) of the data word to 0. when the pd pin is high and the pd bit is set to 1, all dacs work normally with a typical power consumption of 500 m a at 5 v (400 m a at 3 v). in power-down mode, however, the supply current falls to 300 na at 5 v (90 na at 3 v) when all dacs are powered down. not only does the supply current drop, but each output stage is also internally switched from the output of its amplifier, making it open-circuit. this has the advantage that the outputs are three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifiers. the output stage is illustrated in figure 10. resistor string dac power-down circuitry amplifier v out figure 10. output stage during power-down the bias generator, the output amplifiers, the resistor strings, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. in fact, it is pos- sible to load new data to the input registers and dac registers during power-down. the dac outputs will update as soon as the pd pin goes high or the pd bit is reset to 1. the time to exit power-down is typically 2.5 m s for v dd = 5 v and 5 m s when v dd = 3 v. this is the time from the rising edge of the eighth scl pulse or from the rising edge of pd to when the output voltage deviates from its power-down voltage. see tpc 18. applications typical application circuit the ad5306/ad5316/ad5326 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 v to v dd . more typically, these devices are used with a fixed, precision reference voltage. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable external reference would be the ad589, a 1.23 v band gap reference. figure 11 shows a typical setup for the ad5306/ ad5316/ad5326 when using an external reference. note that a0 and a1 can be high or low. 1 f v ref a v ref b v out v in ref 0.1 f 10 f scl sda gnd v out a v out d ad5306/ad5316/ ad5326 serial interface ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v v out c v out b v ref c v ref d a0 a1 ext v dd = 2.5v to 5.5v figure 11. ad5306/ad5316/ad5326 using a 2.5 v external reference
rev. c ?6 ad5306/ad5316/ad5326 driving v dd from the reference voltage if an output range of 0 v to v dd is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference inputs to v dd . as this supply may be noisy and not very accurate, the ad5306/ad5316/ad5326 may be powered from the reference voltage; for example, using a 5 v reference such as the ref195. the ref195 will output a steady supply voltage for the ad5306/ad5316/ad5326. the typical current required from the ref195 is 500 m a supply current and approximately 112 m a to supply the reference inputs (if unbuf- fered). this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the cur- rent to the loads. the total current required (with a 10 k w load on each output) is 612 4 5 10 2 6 m avk ma + () = /. w the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 5.2 ppm (26 m v) for the 2.6 ma current drawn from it. this corresponds to a 0.0013 lsb error at eight bits and 0.021 lsb error at 12 bits. bipolar operation using the ad5306/ad5316/ad5326 the ad5306/ad5316/ad5326 have been designed for single- supply operation, but a bipolar output range is also possible using the circuit in figure 12. this circuit will give an output voltage range of 5 v. rail-to-rail operation at the ampli?r output is achievable using an ad820 or an op295 as the output ampli?r. 1 f v ref a v dd v out a 0.1 f 10 f 5v ad820/ op295 5v +5v r1 10k r2 10k scl a0 2-wire serial interface v out v in gnd ad1585 ?v v out b v out c v out d 6v to 12v v ref b ad5306/ad5316/ ad5326 sda a1 v ref c v ref d gnd figure 12. bipolar operation with the ad5306/ ad5316/ad5326 the output voltage for any input code can be calculated as follows: v refin d r r r refin r r out n = () + () () ? ? ? ? ? 212 121 ? where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input. with: refin = 5 v, r 1 = r 2 = 10 k w : vdv out n = () 10 2 5 / multiple devices on one bus figure 13 shows four ad5306 devices on the same serial bus. each has a different slave address since the states of the a0 and a1 pins are different. this allows each of 16 dacs to be writ- ten to or read from independently. v dd scl a0 pull-up resistors a1 ad5306 sda master scl a0 a1 sda v dd scl sda ad5306 sda v dd ad5306 ad5306 a0 a1 a0 a1 scl figure 13. multiple ad5306 devices on one bus ad5306/ad5316/ad5326 as a digitally programmable wi n dow detector a digitally programmable upper/lower limit detector using two of the dacs in the ad5306/ad5316/ad5326 is shown in figure 14. the upper and lower limits for the test are loaded to dacs a and b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led will indicate the fail condition. similarly, dacs c and d can be used for window detection on a second vin signal. 1/2 ad5306/ad5316/ ad5326 * v ref a v ref b scl sda v dd gnd v out a v out b 5v 0.1 f 10 f scl din v ref v in 1/2 cmp04 1k fail pass/ fail 1k pass 1/6 74hc05 * additional pins omitted for clarity figure 14. window detection coarse and fine adjustment using the ad5306/ad5316/ ad5326 two of the dacs in the ad5306/ad5316/ad5326 can be paired together to form a coarse and fine adjustment function, as shown in figure 15. dac a is used to provide the coarse adjustment while dac b provides the fine adjustment. varying the ratio of r1 and r2 will change the relative effect of the coarse and fine adjustments. with the resistor values and exter- nal reference shown, the output amplifier has unity gain for the dac a output, so the output range is 0 v to 2.5 v ?1 lsb. for dac b, the amplifier has a gain of 7.6 10 ? , giving dac b a range equal to 19 mv. similarly, dacs c and d can be paired together for coarse and fine adjustment. the circuit is shown with a 2.5 v reference, but reference volt- ages up to v dd may be used. the op amps indicated will allow a rail-to-rail output swing.
rev. c ad5306/ad5316/ad5326 ?7 0.1 f v ref a v dd v out a 0.1 f 10 f v dd = 5v ad820/ op295 5v r3 51.2k r4 390 v out v in gnd v out b v ref b 1/2 ad5306/ad5316/ ad5326 gnd v out ext ref r1 390 r2 51.2k ad780/ref192 with v dd = 5v figure 15. coarse/fine adjustment power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5306/ad5316/ad5326 is mounted should be designed so that the analog and digital sections are separated and con?ed to certain areas of the board. if the ad5306/ad5316/ad5326 is in a system where multiple devices require an agnd-to-dgnd connection, the connec- tion should be made at one point only. the star ground point should be established as close as possible to the device. the ad5306/ad5316/ad5326 should have ample supply bypassing of 10 m f in parallel with 0.1 m f on the supply located as close to the package as possible, ideally right up against the device. the 10 m f capacitors are the tantalum bead type. the 0.1 m f capacitor should have low effective series resistance (esr) and effec- tive series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequen- cies, to handle transient currents due to internal logic switching. the power supply lines of the ad5306/ad5316/ad5326 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. a ground line routed between the sda and scl lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). avoid crossover of digital and analog signals. traces on oppo- site sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
rev. c ?8 ad5306/ad5316/ad5326 table i. overview of ad53xx serial devices no. of settling part no. resolution dacs dnl interface time ( s) package pins singles ad5300 8 1 0.25 spi 4 sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.5 spi 7 msop 8 ad5322 12 2 1.0 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.5 spi 7 tssop 16 ad5323 12 2 1.0 spi 8 tssop 16 quads ad5304 8 4 0.25 spi 6 msop 10 ad5314 10 4 0.5 spi 7 msop 10 ad5324 12 4 1.0 spi 8 msop 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.5 2-wire 7 msop 10 ad5325 12 4 1.0 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.5 2-wire 7 tssop 16 ad5326 12 4 1.0 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.5 spi 7 tssop 16 ad5327 12 4 1.0 spi 8 tssop 16 octals ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.5 spi 7 tssop 16 ad5328 12 8 1.0 spi 8 tssop 16 visit www.analog.com/support/standard_linear/selection_guides/ad53xx.html for more information. table ii. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time ( s) additional pin functions package pins singles buf gain hben clr ad5330 8 0.25 1 6 ?? ? tssop 20 ad5331 10 0.5 1 7 ?? tssop 20 ad5340 12 1.0 1 8 ?? ? tssop 24 ad5341 12 1.0 1 8 ?? ? ? tssop 20 duals ad5332 8 0.25 2 6 ? tssop 20 ad5333 10 0.5 2 7 ?? ? tssop 24 ad5342 12 1.0 2 8 ?? ? tssop 28 ad5343 12 1.0 1 8 ?? tssop 20 quads ad5334 8 0.25 2 6 ?? tssop 24 ad5335 10 0.5 2 7 ?? tssop 24 ad5336 10 0.5 4 7 ?? tssop 28 ad5344 12 1.0 4 8 tssop 28
rev. c ad5306/ad5316/ad5326 ?9 outline dimensions 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153ab
rev. c c02066??/03(c) ?0 ad5306/ad5316/ad5326 revision history location page 8/03?ata sheet changed from rev. b to rev. c. added a version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to tpc 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 added octals section to table i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4/01?ata sheet changed from rev. a to rev. b. edit to figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to right/ left section of pointer byte bits section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to input shift register section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 edits to figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 edit to figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.

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